1. Field of the Invention
The present invention relates generally to synchronous dynamic random access memory (SDRAM) technology and more particularly, to techniques for optimizing the operation of a SDRAM for variable length data transfers.
2. Description of the Related Art
Dynamic random access memory (DRAM) is used to provide a number of different functions in computers including: "scratch pad" memory and video frame buffers. A synchronous DRAM or SDRAM is designed to deliver bursts of data at very high speed using automatic addressing, multiple page interleaving, and a synchronous (or clocked) interface.
FIG. 1 is a block diagram illustrating a SDRAM 10 of the prior art. SDRAM 10 includes a control logic unit 12 that receives address, row address select (RAS), column address select (CAS), write enable (WE), and data input/output mask (DQM) assertions which control the operation of the SDRAM. Control logic unit 12 uses the assertions to control a number of memory banks ("banks") 14, which are labeled A-N. Banks 14 receive and transmit data through an output requestor 16 and an input requester 18 to a data bus 20.
FIG. 2A is a flow chart of a prior art method 22 of operating a SDRAM controller in a "fixed length" mode. Method 22 begins at an operation 24, where the SDRAM is programmed into the most common mode, the fixed length mode. A fixed length of transfer of 1, 2, 4, or 8 data phases is chosen during the mode register select (MRS) cycle. Then, an operation 26 optimizes the burst transfers for same bank transactions which is ideal for computer applications because computers process data in bursts that are often sequential and defined at a fixed length.
Optimization may include a SDRAM feature called auto refresh. Because SDRAM memory cells are capacitive, the charge they contain dissipates with time. As the charge is lost, so is the data in the memory cells. To prevent this from happening, SDRAMs must be refreshed by restoring the charge on the individual memory cells periodically. In addition, the SDRAM may use a feature called auto precharge, which allows the memory chip's circuitry to close a page automatically at the end of a burst. Auto precharge can be used because the burst transfers are of a fixed length, and it is known when the transfers will terminate.
FIG. 2B is a flow chart of a prior art method 28 of operating a SDRAM controller in "variable length" mode. Variable length mode is required in applications that do not use the 1, 2, 4, or 8 data phase transaction set available from the fixed mode. The method 28 begins with an operation 30 where the SDRAM is programmed in variable length mode. The variable length mode of the SDRAM, which is also known as full page length mode, is used to accommodate applications with long streams of data, such as those that are present in DMA and video. After the SDRAM is programmed, an operation 32 optimizes the burst transfers for multiple bank transactions.
FIG. 2C is a flow chart of a alternative prior art method 34 of operating a SDRAM controller in a variable length mode. The method 34 begins at operation 30 where the SDRAM is programmed in variable length mode. Then, an operation 36 optimizes the burst transfers for same bank transactions.
While the above methods 28 and 34 arc adequately able to handle applications such as using DMA for a frame buffer or streaming data off of a disk drive system and buffering data into RAM, they are inefficient for applications where the length of the data bursts varies from short to long lengths. When the bursts vary between lengths, it becomes very difficult for the SDRAM to determine when to terminate the transaction.
Furthermore, methods 28 and 34 are also inefficient for applications that require the SDRAM to service multiple requestors. In such scenarios, prior art methods would only be able to handle one request at a time in same bank situations, forcing the other requests to wait, even as the SDRAM experiences idle cycles. In view of the foregoing, it is desirable to have methods and an apparatus that is able to optimizes the burst transfer lengths to requesters' different characteristics, and at the same time allowing the data bus to change to a different transaction with minimal idle time on the bus.